Flash memory devices are a well known type of semiconductor memory device. In a programming mode, charges are stored via tunneling in a floating gate of a flash memory device to store data in the flash memory device. In an erasing mode, charges are discharged from the floating gate. Flash memory devices may have high integration density, low power consumption, and strong endurance against external shocks or stresses. As a result, they are increasingly used in various applications such as in mobile electronic devices.
FIG. 1 is a cross-sectional diagram showing cell bias voltages for an erasing operation in a flash memory cell. As shown in FIG. 1, the flash memory cell includes a control gate (CG) 10, a floating gate (FG) 20, a source region 30a, a drain region 30b, and a P-well 40 that forms a channel in a bulk region of the device. An oxide/nitride/oxide (ONO) dielectric film that may have a large coupling capacitance is provided between the control gate 10 and the floating gate 20. A tunnel oxide film is interposed between the floating gate 20 and the P-well 40 to facilitate Fowler-Nordheim tunneling (F-N tunneling). Thus, as shown in FIG. 1, there is capacitance C1 through the dielectric film between the control gate 10 and the floating gate 20, and there is tunnel capacitance C2 through the tunnel oxide film between the floating gate 20 and the P-well 40. Through the selection of the capacitances C1 and C2, it is possible to divide bias voltages for programming, erasing, and reading voltages. In erasing data from the flash memory cell, a wordline voltage VWL of, for example, about 0V is applied to the control gate 10, while an erasing voltage Vera of, for example, about 20V is applied to the bulk region 40. Under this bias condition, electrons move from the floating gate 20 toward the P-well 40 through the tunnel oxide film by way of the F-N tunneling effect induced by a DC voltage distributed at the tunnel capacitance C2. Table 1 below summarizes a bias condition of voltages applied to a memory cell block (herein the term “block” may comprise any grouping of memory cells such as, for example, any block, sector or array of memory cells) during such an erasing operation.
TABLE 1Wordline (WL)0Selected transistor (SSL/GSL)FCommon source line (CSL)FBitline (BL)FP-well (bulk region)Vera
In Table 1, the symbol ‘F’ means a floating state. Under the bias condition shown in the Table 1, the migration of electrons from the floating gate 20 to the P-well 40 by the tunneling effect is dependent on a tunneling voltage Vtun that is distributed between the P-well 40 and the floating gate 20. The tunneling voltage Vtun is determined by the capacitance C1 between the control gate 10 and the floating gate 20, and the tunnel capacitance C2 between the floating gate 20 and the P-well 40. The tunnel capacitance C2 is the sum of all capacitive factors between layers in adjacent floating gates and the bulk region of the device. An erasure-coupling ratio αera, which is a factor representing a ratio of voltages contributing to the tunneling effect during the erasing operation, is given by Equation 1.
                              α          era                =                              C            2                                              C              1                        +                          C              2                                                          [                  Equation          ⁢                                          ⁢          1                ]            
The potential of the floating gate (VFG) is a function of the erasure-coupling ratio as shown in Equation 2.VFG=(Vera−VWL)×αera  [Equation 2]
The tunneling voltage Vtun is distributed in the dimension set by subtracting the potential VFG from the erasing voltage Vera that is applied to the bulk region or P-well 40, as shown in Equation 3.Vtun=(Vera−VFG)  [Equation 3]
If the erasure-coupling ratio αera is uniform over all of the memory cells in a unit block, electrons are uniformly discharged from the floating gate by the equivalent distribution with the same tunneling voltage Vtun according to the same erasing voltage under the bias conditions shown in Table 1. Thus, the memory cells after the erasing operation may have a narrow threshold-voltage distribution profile. However, the erasure-coupling ratio αera may be variable across memory cells in a unit block because of, for example, irregular wordline widths and pitches due to variations in wordline patterns and/or processing conditions. These variations in the erasure-coupling ratio may result in different threshold voltages, after the erasing operation, by memory cells or unit pages each sharing the same wordline. The deviations in the erasure-coupling ratio αera may thus generate a widely spread distribution profile of threshold voltages over the memory device.
FIG. 2 is a graph depicting the threshold-voltage distribution profile, after the erasing operation, that may result due to deviations in the erasure-coupling ratios by memory cells or pages. In particular, FIG. 2 shows a threshold-voltage distribution profile 100 of the programmed state for general flash memory cells, and the post-erasing threshold-voltage distribution profile 110, 120, 130 of the memory cells in a flash memory device.
As shown in FIG. 2, the threshold-voltage distribution pattern after the erasing operation under the bias condition shown in Table 1 exhibits a wider distribution profile 110, 120, 130 as compared to the programming distribution profile 100. This wider threshold-voltage distribution profile arises because of the variations between the erasure-coupling ratios, which results in differences in the erasure speeds of the memory cells. In particular, there are over-erased cells that are located in the distribution profile 130 under a preferred lower limit Voe (i.e., lower than the proper post-erasing distribution profile 120, and under-erased cells 110, which are located in the distribution profile 110 over the preferred upper limit Vde (i.e., higher than the proper post-erasing distribution profile 120, due to inefficient tunneling effects by small tunneling voltages. The over-erased cells are referred to as fast-erased cells, while the under-erased cells are referred to as slow-erased cells. The fast-erased and slow-erased cells result in the wider threshold-voltage distribution profile, even though the same erasing voltage Vera is applied to the memory cells. The slow-erased cells have small erasure-coupling ratios (αera), and hence relatively lower voltages for the tunneling effect. As a result, it takes a longer period of time for sufficient electrons to be released from the floating gates 20 to the P-well 40 (for the same erasing voltage Vera) as compared to other memory cells. In the fast-erased cells, the erasure-coupling ratios (αera) are larger than other cells in the same block or sector, and hence electrons are more easily released (for the same erasing voltage Vera) from the floating gates 20 to the P-well 40. The spread of the post-erasing threshold-voltage distribution profile means that the speed with which the memory cells are erased differs.